NXP Semiconductors /MIMXRT1021 /IOMUXC /SW_MUX_CTL_PAD_GPIO_EMC_07

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SW_MUX_CTL_PAD_GPIO_EMC_07

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ALT0)MUX_MODE 0 (DISABLED)SION

SION=DISABLED, MUX_MODE=ALT0

Description

SW_MUX_CTL_PAD_GPIO_EMC_07 SW MUX Control Register

Fields

MUX_MODE

MUX Mode Select Field.

0 (ALT0): Select mux mode: ALT0 mux port: SEMC_DATA07 of instance: semc

1 (ALT1): Select mux mode: ALT1 mux port: XBAR1_INOUT07 of instance: xbar1

2 (ALT2): Select mux mode: ALT2 mux port: LPUART3_RX of instance: lpuart3

3 (ALT3): Select mux mode: ALT3 mux port: SAI2_RX_SYNC of instance: sai2

4 (ALT4): Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO19 of instance: flexio1

5 (ALT5): Select mux mode: ALT5 mux port: GPIO2_IO07 of instance: gpio2

SION

Software Input On Field.

0 (DISABLED): Input Path is determined by functionality

1 (ENABLED): Force input path of pad GPIO_EMC_07

Links

() ()